1 00:00:00,960 --> 00:00:02,940 Now we get to the fun part! 2 00:00:02,940 --> 00:00:07,990 To build other logic gates, we'll design complementary pullup and pulldown circuits, hooked up as 3 00:00:07,990 --> 00:00:12,760 shown in the diagram on the right, to control the voltage of the output node. 4 00:00:12,760 --> 00:00:17,449 "Complementary" refers to property that when one of the circuits is conducting, the other 5 00:00:17,449 --> 00:00:19,589 is not. 6 00:00:19,589 --> 00:00:24,169 When the pullup circuit is conducting and the pulldown circuit is not, the output node 7 00:00:24,169 --> 00:00:30,009 has a connection to V_DD and its output voltage will quickly rise to become a valid digital 8 00:00:30,009 --> 00:00:31,779 1 output. 9 00:00:31,779 --> 00:00:36,790 Similarly, when the pulldown circuit is conducting and the pullup is not, the output node has 10 00:00:36,790 --> 00:00:41,309 a connection to GROUND and its output voltage will quickly fall to become a valid digital 11 00:00:41,309 --> 00:00:43,739 0 output. 12 00:00:43,739 --> 00:00:47,730 If the circuits are incorrectly designed so that they are not complementary and could 13 00:00:47,730 --> 00:00:53,600 both be conducting for an extended period of time, there's a path between V_DD and GROUND 14 00:00:53,600 --> 00:00:58,390 and large amounts of short circuit current will flow, a very bad idea. 15 00:00:58,390 --> 00:01:02,699 Since our simple switch model won't let us determine the output voltage in this case, 16 00:01:02,699 --> 00:01:06,780 we'll call this output value "X" or unknown. 17 00:01:06,780 --> 00:01:12,470 Another possibility with a non-complementary pullup and pulldown is that neither is conducting 18 00:01:12,470 --> 00:01:16,080 and the output node has no connection to either power supply voltage. 19 00:01:16,080 --> 00:01:21,020 At this point, the output node is electrically floating and whatever charge is stored by 20 00:01:21,020 --> 00:01:25,210 the nodal capacitance will stay there, at least for a while. 21 00:01:25,210 --> 00:01:30,560 This is a form of memory and we'll come back to this in a couple of lectures. 22 00:01:30,560 --> 00:01:34,770 For now, we'll concentrate on the behavior of devices with complementary pullups and 23 00:01:34,770 --> 00:01:37,189 pulldowns. 24 00:01:37,189 --> 00:01:41,899 Since the pullup and pulldown circuits are complementary, we'll see there's a nice symmetry 25 00:01:41,899 --> 00:01:43,689 in their design. 26 00:01:43,689 --> 00:01:48,689 We've already seen the simplest complementary circuit: a single NFET pulldown and a single 27 00:01:48,689 --> 00:01:50,729 PFET pullup. 28 00:01:50,729 --> 00:01:55,640 If the same signal controls both switches, it's easy to see that when one switch is on, 29 00:01:55,640 --> 00:01:58,700 the other switch is off. 30 00:01:58,700 --> 00:02:03,759 Now consider a pulldown circuit consisting of two NFET switches in series. 31 00:02:03,759 --> 00:02:08,470 There's a connection through both switches when A is 1 and B is 1. 32 00:02:08,470 --> 00:02:13,750 For any other combination of A and B values, one or the other of the switches (or both!) 33 00:02:13,750 --> 00:02:15,890 will be off. 34 00:02:15,890 --> 00:02:21,790 The complementary circuit to NFET switches in series is PFET switches in parallel. 35 00:02:21,790 --> 00:02:26,390 There's a connection between the top and bottom circuit nodes when either of the PFET switches 36 00:02:26,390 --> 00:02:31,980 is on, i.e., when A is 0 or B is 0. 37 00:02:31,980 --> 00:02:40,440 As a thought experiment consider all possible pairs of values for A and B: 00, 01, 10, and 38 00:02:40,440 --> 00:02:42,090 11. 39 00:02:42,090 --> 00:02:48,400 When one or both of the inputs is 0, the series NFET circuit is not conducting and parallel 40 00:02:48,400 --> 00:02:50,470 PFET circuit is. 41 00:02:50,470 --> 00:02:56,370 And when both inputs are 1, the series NFET circuit is conducting but the parallel PFET 42 00:02:56,370 --> 00:02:59,500 circuit is not. 43 00:02:59,500 --> 00:03:04,540 Finally consider the case where we have parallel NFETs and series PFETs. 44 00:03:04,540 --> 00:03:07,900 Conduct the same thought experiment as above to convince yourself that when one of the 45 00:03:07,900 --> 00:03:11,600 circuits is conducting the other isn't. 46 00:03:11,600 --> 00:03:17,090 Let's put these observations to work when building our next CMOS combinational device. 47 00:03:17,090 --> 00:03:23,370 In this device, we're using series NFETs in the pulldown and parallel PFETs in the pullup, 48 00:03:23,370 --> 00:03:28,320 circuits that we convinced ourselves were complementary in the previous slide. 49 00:03:28,320 --> 00:03:32,990 We can build a tabular representation, called a truth table, that describes the value of 50 00:03:32,990 --> 00:03:38,450 Z for all possible combinations of the input values for A and B. 51 00:03:38,450 --> 00:03:45,311 When A and B are 0, the PFETs are on and the NFETs are off, so Z is connected to V_DD and 52 00:03:45,311 --> 00:03:48,040 the output of the device is a digital 1. 53 00:03:48,040 --> 00:03:54,100 In fact, if either A or B is 0 [CLICK, CLICK] that continues to be the case, and the value 54 00:03:54,100 --> 00:03:56,540 of Z is still 1. 55 00:03:56,540 --> 00:04:01,790 Only when both A and B are 1 [CLICK], will both NFETs be on and the value of Z become 56 00:04:01,790 --> 00:04:03,120 0. 57 00:04:03,120 --> 00:04:08,140 This particular device is called a NAND gate, short for "NOT-AND", a function that is the 58 00:04:08,140 --> 00:04:11,620 inverse of the AND function. 59 00:04:11,620 --> 00:04:16,100 Returning to a physical view for a moment, the figure on the left is a bird's eye view, 60 00:04:16,100 --> 00:04:20,370 looking down on the surface of the integrated circuit, showing how the MOSFETs are laid 61 00:04:20,370 --> 00:04:22,350 out in two dimensions. 62 00:04:22,350 --> 00:04:27,969 The blue material represents metal wires with large top and bottom metal runs connecting 63 00:04:27,969 --> 00:04:30,550 to V_DD and GROUND. 64 00:04:30,550 --> 00:04:35,900 The red material forms the polysilicon gate nodes, the green material the n-type source/drain 65 00:04:35,900 --> 00:04:40,930 diffusions for the NFETs and the tan material the p-type source/drain diffusions for the 66 00:04:40,930 --> 00:04:41,930 PFETs. 67 00:04:41,930 --> 00:04:48,210 Can you see that the NFETs are connected in series and the PFETs in parallel? 68 00:04:48,210 --> 00:04:54,439 Just to give you a sense of the costs of making a single NAND gate, the yellow box is a back-of-the-envelope 69 00:04:54,439 --> 00:05:00,690 calculation showing that we can manufacture approximately 26 billion NAND gates on a single 70 00:05:00,690 --> 00:05:07,620 300mm (that's 12 inches for us non-metric folks) silicon wafer. 71 00:05:07,620 --> 00:05:13,800 For the older IC manufacturing process shown here, it costs about $3500 to buy the materials 72 00:05:13,800 --> 00:05:19,710 and perform the manufacturing steps needed to form the circuitry for all those NAND gates. 73 00:05:19,710 --> 00:05:23,849 So the final cost is a bit more than 100 nano-dollars per NAND gate. 74 00:05:23,849 --> 00:05:26,830 I think this qualifies as both cheap and small!