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Serial point-to-point links
are the modern replacement

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for the parallel
communications bus

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with all its electrical
and timing issues.

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0..08 Each link is
unidirectional and has only

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a single driver and the receiver
recovers the clock signal from

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the data stream, so there are
no complications from sharing

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the channel, clock skew,
and electrical problems.

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The very controlled electrical
environment enables very high

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signaling rates, well up into
the gigahertz range using

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today’s technologies.

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If more throughput
is needed, you

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can use multiple serial
links in parallel.

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Extra logic is needed to
reassemble the original data

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from multiple packets sent in
parallel over multiple links,

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but the cost of the
required logic gates

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is very modest in
current technologies.

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Note that the expansion
strategy of modern systems

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still uses the notion
of an add-in card that

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plugs into the motherboard.

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But instead of connecting
to a parallel bus,

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the add-in card
connects to one or more

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point-to-point
communication links.

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Here’s the system-level
communications diagram

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for a recent system based on
an Intel Core i7 CPU chip.

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The CPU is connected
directly to the memories

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for the highest-possible
memory bandwidth,

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but talks to all
the other components

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over the QuickPath
Interconnect (QPI),

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which has 20
differential signaling

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paths in each direction.

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QPI supports up to 6.4
billion 20-bit transfers

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in each direction every second.

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All the other
communication channels

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(USB, PCIe, networks,
Serial ATA, Audio, etc.)

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are also serial links,
providing various communication

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bandwidths depending
on the application.

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Reading about the QPI
channel used by the CPU

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reminded me a lot
of the one ring

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that could be used
to control all

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of Middle Earth in the Tolkien
trilogy Lord of the Rings.

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Why mess around with a lot
of specialized communication

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channels when you have a single
solution that’s powerful enough

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to solve all your
communication needs?

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PCI Express (PCIe) is often
used as the communication

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link between components
on the system motherboard.

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A single PCIe version 2 “lane”
transmits data at 5 Gb/sec

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using low-voltage differential
signaling (LVDS) over wires

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designed to have a 100-Ohm
characteristic impedance.

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The PCIe lane is
under the control

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of the same sort of network
stack as described earlier.

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The physical layer transmits
packet data through the wire.

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Each packet starts with
a training sequence

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to synchronize the receiver’s
clock-recovery circuitry,

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followed by a unique
start sequence,

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then the packet’s data payload,
and ends with a unique end

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sequence.

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The physical layer payload is
organized as a sequence number,

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a transaction-layer payload
and a cyclical redundancy check

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sequence that’s used
to validate the data.

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Using the sequence number,
the data link layer

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can tell when a packet
has been dropped

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and request the transmitter
restart transmission

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at the missing packet.

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It also deals with
flow control issues.

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Finally, the transaction
layer reassembles the message

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from the transaction layer
payloads from all the lanes

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and uses the header to identify
the intended recipient at the

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receive end.

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Altogether, a significant amount
of logic is needed to send

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and receive messages
on multiple PCIe lanes,

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but the cost is quite acceptable
when using today’s integrated

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circuit technologies.

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Using 8 lanes, the maximum
transfer rate is 4 GB/sec,

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capable of satisfying the needs
of high-performance peripherals

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such as graphics cards.

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So knowledge from
the networking world

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has reshaped how components
communicate on the motherboard,

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driving the transition
from parallel buses

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to a handful of serial
point-to-point links.

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As a result today’s systems
are faster, more reliable,

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more energy-efficient and
smaller than ever before.